The invention relates to a voltage regulator, such as a linear voltage regulator.
A DC-to-DC voltage regulator typically is used to convert a DC input voltage to either a higher or a lower DC output voltage. One type of voltage regulator, called a linear regulator, is often chosen due to its simplistic design. As an example, referring to FIG. 1, a linear regulator 10 may use a transistor 20 to conduct current from an input voltage source 9 (providing a voltage called V.sub.IN) to a load 23 that is coupled to an output terminal 19 of the regulator 10. To regulate an output voltage (called V.sub.OUT), the regulator 10 may include an error amplifier 12 that amplifies the difference between a reference voltage (called V.sub.REF) and a signal (called V.sub.F) that is proportional to the V.sub.OUT voltage. Due to the negative feedback, an error voltage (called V.sub.ERR) that is provided by the amplifier 12 functions to control the transistor 20 in a manner to keep the V.sub.OUT voltage within prescribed limits. The reference voltage V.sub.REF may be provided by, for example, a low power voltage reference circuit 14. Other features of the regulator 20 may include a resistor divider (formed from resistors 16 and 18) that receives the V.sub.OUT voltage and provides the V.sub.F voltage.
When the regulator 10 powers up, the voltages and currents of the regulator 10 fluctuate until the voltages and currents reach steady state, or quiescent, bias levels. Unfortunately, these fluctuations may produce power surges that cause the V.sub.IN and V.sub.OUT voltages to vary outside of specified tolerances. For example, the V.sub.IN and V.sub.OUT voltages may be supplied by voltage rails of a computer system power supply and may each not be able to vary beyond a predetermined percentage (five percent, for example) of a predetermined voltage level (five volts, for example).
To minimize the effects that the regulator 10 imposes on the input voltage source 9 during powerup, a limitation may be placed on a slew rate of the regulator 10. In particular, the slew rate is the maximum rate at which the regulator 10 can change the V.sub.OUT voltage. By limiting the slew rate, voltage and current fluctuations, such as a fluctuation 32 (see FIG. 2) in the V.sub.OUT voltage, are dampened when the regulator 10 powers up.
One way to suppress the slew rate of the regulator 10 is to couple a capacitor 22 (see FIG. 1) between the output terminal 19 and ground. In this manner, because the output current of the regulator 10 is limited, an upper limit is placed on a rate at which the regulator 10 may charge and discharge the capacitor. Thus, this upper limit establishes the slew rate of the regulator 10 and may be significantly lower than the slew rate of the regulator 10 without the capacitor 22. Unfortunately, designs that limit the slew rate for purposes of regulating the powerup state of the regulator 10 may cause the regulator 10 to respond poorly to transient load conditions during normal operation of the regulator 10.
Thus, there is a continuing need for a regulator having a slew rate to accommodate the state of the regulator.